Computer systems and other digital systems often include a large number of very large scaled integrated (VLSI) circuits that are connected by a single segment or multi-segment transmission line for binary communications. Drivers and receivers interface between these VLSI circuits and the transmission lines. Gunning Transceiver Logic (GTL) for input and output structures has been designed to provide a low-swing interface in these high-speed digital systems. An objective of the GTL interface standard is to improve the performance of high speed digital systems by reducing the difference between the logic high voltage level and the logic low voltage level. Gunning (U.S. Pat. No. 5,023,488, which is incorporated by reference herein) discloses such GTL drivers and receivers for interfacing VLSI CMOS circuits to transmission lines. The nominal voltage swing of GTL is approximately 0.3 Volts (logic low) to 1.2 Volts (logic high).
A GTL output driver is an open-drain N-channel device which, when turned off, is pulled up to the output supply voltage and, when turned on, the device can sink up to 40 mA of current at a maximum output voltage of 0.4V. The output driver is designed for a doubly-terminated 50 Ω transmission line.
More particularly FIG. 1 displays a known GTL driver 30 that is disclosed in Gunning. A very wide channel, open drain, N-channel CMOS transistor M1 is used for transforming binary signals to a transmission line 32 from a more or less conventional CMOS signal source 34 which effectively isolates the transmission line 32 from the ordinary 5 v rail-to-rail signal swing of the signal source 34. Transistor M1 has its gate connected to the output of the signal source 34, its drain connected to the transmission line 32, and its source returned to ground (i.e., the same reference level as the 0 v rail of the signal source 34). The channel width of the transistor M1 is orders of magnitude greater than its channel length to reduce the effective resistance of its source-drain circuit in conduction.
In operation, when the signal at VIN, drops to a low (“0”) logic level, transistors M2 and M3 are switched into and out of conduction, respectively. Thus, the gate capacitance of transistor M1 is charged relatively rapidly by the current conducted by the source-drain circuit of transistor M2. The gate of transistor M1 is quickly pulled up toward the 5 Volt rail of the signal source 14, thereby causing transistor M1 to promptly switch into conduction. On the other hand, when the signal VIN increases to a high (“1”) logic level, transistor M2 switches out of conduction while transistor M3 switches into conduction. This causes the gate capacitance of transistor M1 to be quickly discharged by the current conducted by the source-drain circuit of transistor M3 so that the gate of transistor M1 is pulled down relatively rapidly toward the 0 Volt rail of the signal source 14, thereby promptly switching transistor M1 out of conduction.
The signal level on the transmission line 32 tends to stabilize substantially at the voltage level to which the transmission line 32 is terminated a short time after transistor M1 is switched out of conduction (i.e., as soon as the switching transients have settled out). On the other hand, when transistor M1 is switched into conduction, its source-drain circuit provides a ground return path for current flow through the parallel terminating resistors indicated by 36. The signal level at which the transmission line 32 tends to stabilize (again, after the switching transients have settled out) is determined by the voltage division which the parallel terminating resistor 36 and the source-drain resistance of the conductive transistor M1 perform on the voltage to which the transmission line 32 is terminated.
Provision is made in the driver 30 for damping certain of the switching transients which are generated when transistor M1 is switched into and out of conduction. Some of the more troublesome switching transients occur when transistor M1 is switched from a conductive state to a non-conductive state. The drain-side parasitic packaging inductance and the drain-side parasitic capacitances of transistor M1 form a ringing circuit which tends to cause the voltage on the transmission line 32 to overshoot its nominal upper limit by a substantial margin and to oscillate for a prolonged period of time. Similarly, the source-side parasitic inductances and capacitances of transistor M1 form another ringing circuit which tends to cause a potentially troublesome oscillatory “ground bounce” perturbance of the reference voltage on the low level rail of the CMOS circuit.
To reduce these switching transients, the driver 30 is equipped with a feedback circuit for briefly connecting the drain of transistor M1 to its gate when transistor M1 is switched from a conductive state to a non-conductive state. The feedback circuit includes a pair of n-channel transistors M4 and M5 which have their source-drain circuits connected in series between the drain and gate of transistor M1. The input VIN for the driver 30 is coupled to the gate of transistor M5, and two additional inverter stages 37 and 38 are coupled between the inverter 34 and the gate of transistor M4.
Most GTL output circuits include a means to control output slew rates. Internal signals must transition fairly slowly to accomplish having controlled output slew rates. As frequency increases, however, the signals present at internal nodes within the GTL output circuit do not have enough time to make a normal full transition. As a result, slew rate control is impacted when these internal signals do not start from a desired level.
Thereby, a need exists for slew rate control of the internal nodes of the GTL driver. Conventional approaches for incorporating slew rate control at higher frequencies, however, use passive components only and, thereby, a slow rise and fall RC time constant exists that controls the output transistors. Accordingly, there is a substantial waiting period for the slow RC time constant in bringing the output node of the transmission line driver up to the power supply rail (VCC) or down to ground (GND). Moreover, as a result, internal nodes within the output driver begin at a point somewhere between the power supply rail VCC and ground GND. Thereby, an effective slew rate control at the output does not exist and, as a result, the output can rise too fast which can cause signal integrity problems. In the alternative, duty cycle problems arise where the delay to the output from the input signal might vary from that which is normally expected. Accordingly, duty cycle issues exist. For example, give a clocked system that must maintain a 50% duty cycle, unfortunately, one edge of the output signal may start to speed up which will lead to an actual 60% duty cycle. The objective of most designers is to maintain the same propagation delay from input to output to prevent these duty cycle problems.
Thus, there is a need for a GTL transmission line driver that provides an output voltage swing of approximately 0.3 Volts (logic low) to 1.2 Volts (logic high) and that overcomes the problems of a modified duty cycle and the loss of slew rate control of the conventional GTL driver discussed above.
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.